1. Field of the Invention
The invention relates to a phase change memory and, in particular, to a sensing circuit of a phase change memory.
2. Description of the Related Art
FIG. 1 is a conventional sensing circuit of a phase change memory. In FIG. 1, a current IR flows through a phase change memory cell 115. Since resistance of the phase change memory cell 115 changes with a storage state thereof, a voltage drop generated across the phase change memory cell 115 by the current IR also changes. The voltage drop is transferred to a compartor 130 and compared with a reference voltage VREF such that a storage state of the phase change memory 115 is detected. Generally, the comparator 130 is an analog circuit which is designed to detect small differences. Since RC loading of a bit line delays the process of converting a current to a voltage, reading speed is slowed down.
FIG. 2 is a sensing circuit of a phase change memory disclosed in U.S. Pat. No. 5,787,042. In FIG. 2, data bit lines is pre-charged to Vdd/2 and an equalizer is then disconnected. Voltages of the data bit lines migrate to opposite directions from the pre-charge voltage and a logic value of data is read out. Since the sensing circuit therein is a latch, two input terminals thereof are coupled to the complementary bit lines and receive differential signals to provide an adequate sensing margin. As a result, two memory cells are required to store a data bit and area required is twice that of a memory array which only requires a single memory cell to store a data bit.